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SRAM

The CMOS IC Team designed and implemented a 64-bit asynchronous SRAM. This project involved mixed signal IC design and members quickly gained experience in simulation and layout through the use of Cadence design tools. While the SRAM project exceeded the complexity of typical SRAM projects offered in 4th year IC courses, the SRAM team members ranged all the way from 1st to 4th year.

Our goal was to perform layout and gain exposure to the challenges of physically constructing transistors and interconnects and create a circuit that behaves as close to simulation as possible. As the second phase of all our projects is the fabrication phase, the design will naturally be taped out in August and characterized upon its return.

Project Target

(full design and layout) Summer 2006

Project Components

  • Cell:
    • Christopher Sue and Nam Rajagopal
  • Decoder:
    • Keith Concessao
  • Sense Amp:
    • Christopher Sue and Junette Tan

References

Internal site: SRAM Wiki
This is a sample SRAM project report with some pictures of how each component might look when laid out in silicon:One KByte SRAM chip Prototype Report
Here are course slides from other universities:CSE 477
SRAM Cell and Column Design
E&CE 438:Dr. Anis\’ slides
Textbook (see Chapter 11 for information on SRAMs)